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  october 1998 f ds693 0 a dual n-c hannel, logic level, powertrench tm mosfet general description features absolute maximum ratings t a = 25 o c unless otherwise noted symbol parameter f ds693 0 a units v dss drain-source voltage 30 v v gss gate-source voltage 20 v i d drain current - continuous (note 1a) 5.5 a - pulsed 2 0 p d power dissipation for dual operation (note 1) 2 w power dissipation for single operation (note 1a) 1.6 w (note 1b) 1 (note 1c) 0.9 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a ) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 40 c/w fds693 0 a rev.d 5.5 a, 3 0 v. r ds(on ) = 0.040 w @ v gs = 10 v r ds(on ) = 0.055 w @ v gs = 4.5 v . fast switching speed . low gate charge (typical 5 nc). high performance t rench technology for extremely low r ds(on) . high power and current handling capability. sot-23 supersot t m -8 soic-16 so-8 sot-223 supersot t m -6 these n-channel logic level mosfets are produced using fairchild semiconductor 's advanced powertrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance . these devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. s1 d1 s2 g1 so-8 d2 d2 d1 g2 fds 6930a pin 1 1 5 7 8 2 3 4 6 ? 1998 fairchild semiconductor corporation
electrical characteristics ( t a = 25 o c unless otherwise noted ) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 20 mv/ o c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a t j = 5 5c 10 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.5 3 v d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c -4 mv/ o c r ds(on) static drain-source on-resistance v gs = 10 v, i d = 5.5 a 0.032 0.04 w t j =12 5c 0.048 0.068 v gs = 4.5 v, i d = 4.8 a 0.044 0.055 i d(on) on-state drain current v gs = 10 v, v ds = 5 v 20 a g fs forward transconductance v ds = 15 v, i d = 5.5 a 12 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 460 pf c oss output capacitance 115 pf c rss reverse transfer capacitance 45 pf switching ch aracteristics (note 2) t d(on ) turn - on delay time v ds = 15 v, i d = 1 a 5 11 ns t r turn - on rise time v gs = 10 v , r gen = 6 w 8 17 ns t d(off) turn - off delay time 17 28 ns t f turn - off fall time 13 24 ns q g total gate charge v ds = 5 v, i d = 5.5 a, 5 7 nc q gs gate-source charge v gs = 5 v 2 nc q gd gate-drain charge 0.9 nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current 1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.3 a (note 2 ) 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fds693 0 a rev.d c. 13 5 o c/w on a 0.003 in 2 pad of 2oz copper. b . 12 5 o c/w on a 0.02 in 2 pad of 2oz copper. a . 78 o c/w on a 0.5 in 2 pad of 2oz copper.
fds693 0 a rev.d 0 1 2 3 4 5 0 6 12 18 24 30 v , drain-source voltage (v) i , drain-source current (a) ds d 3.5v 3.0v v =10v gs 4.0v 5.0v 4.5v 6.0v typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = 10v gs i = 5.5a d figure 3. on-resistance variation with temperature . 1 2 3 4 5 0 3 6 9 12 15 v , gate to source voltage (v) i , drain current (a) v =5.0v ds gs d t = -55c j 125c 25c figure 5 . transfer characteristics. figure 6 . body diode forward voltage varia tion with source current and temperature. figure 4 . on-resistance variation with gate-to -source voltage. 0 6 12 18 24 30 0 1 2 3 4 i , drain current (a) drain-source on-resistance d v = 3.0v gs r , normalized ds(on) 10v 4.0 v 3.5 v 5.5 v 4.5 v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.001 0.01 0.1 1 20 v , body diode forward voltage (v) i , reverse drain current (a) 25c -55c v = 0v gs sd s t = 125c j 2 4 6 8 10 0 0.05 0.1 0.15 0.2 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) 125c 25c i = 2.5a d
fds693 0 a rev.d figure 10. single pulse maximum power dissipation . figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area . typical electrical characteristics 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t /t 1 2 r (t) = r(t) * r r =135 c/w q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 11 . transient thermal response curve . thermal characterization performed using the conditions described in n ote 1c. transient thermal response will change depending on the circuit board design. 0 2 4 6 8 10 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs i = 5.5a d v = 5v ds 10v 15v 0.1 0.2 0.5 1 2 5 10 30 50 100 200 500 1000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss 0.1 0.5 1 2 5 10 30 50 0.01 0.05 0.5 2 10 50 100 v , drain-source voltage (v) i , drain current (a) rds(on) limit d a dc ds 1s 100ms 10ms 1ms 10s v =10v single pulse r =135c/w t =25c q ja gs a 100us 0.01 0.1 0.5 10 50 100 300 0 5 10 15 20 25 30 single pulse time (sec) power (w) single pulse r =135 c/w t = 25c q ja a
trademarks acex? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast ? fastr? gto? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. tinylogic? uhc? vcx? isoplanar? microwire? pop? powertrench? qfet? qs? quiet series? supersot?-3 supersot?-6 supersot?-8


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